1. Field of the Invention
The present general inventive concept relates to a memory device and a method of manufacturing a memory device. More particularly, the present general inventive concept relates to a memory device including a conductive material capable of being bent by an electric field and a method of manufacturing a memory device including a conductive material capable of being bent by an electric field.
2. Description of the Related Art
In general, memory devices may be divided into volatile memory devices and non-volatile devices. The volatile memory device, for example, a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device, has a relatively fast response speed while losing data stored therein when an applied power is off. The non-volatile memory device such as an erasable programmable read only memory (EPROM) device or an electrically erasable programmable read only memory (EEPROM) device has a relatively slow response speed while maintaining data stored therein even though an applied power is off.
A conventional memory device includes a metal oxide semiconductor field effect transistor (MOSFET) manufactured by a metal oxide semiconductor technology. For example, the conventional memory device includes a stacked gate type transistor formed on a silicon substrate, or a trench gate type transistor buried in a silicon substrate. In the conventional MOSFET, a predetermined channel length and a channel width are ensured in order to prevent a short channel effect. Additionally, a gate insulation layer between a substrate and a gate electrode becomes considerably thin as a result of size reduction of the MOSFET. Thus, the conventional MOSFET may not be properly employed in a recent memory device having a critical dimension of nano meter.
Considering above-mentioned problems, novel devices have been developed instead of the conventional MOSFET. That is, a micro electromechanical system (MEMS) and a nano electromechanical system (NEMS) are applied for manufacturing novel semiconductor devices. For example, U.S. Patent Application Publication No. 2004/0181630 discloses a memory device including a carbon nanotube.
In the memory device according to the above U.S. patent application Publication, data may be stored or erased by contacting a carbon nanotube fabric with an upper electrode or a lower electrode. However, the conventional memory device including the carbon nanotube also has some problems as follows.
When the fabric of the carbon nanotube makes contact with the lower electrode, a high voltage is applied to the carbon nanotube fabric and the lower electrode so as to overcome a tension of the carbon nanotube fabric having lateral portions supported by a nitride layer on an insulating interlayer. Thus, a power consumption of the memory device may greatly increase.
Further, van der Waals forces may remarkably effect the carbon nanotube fabric and the lower electrode or the upper electrode when distances between the lower electrode and the carbon nanotube fabric or the upper electrode and the carbon nanotube fabric is maintained in nano scales. Accordingly, the lower electrode or the upper electrode may not easily separate from the carbon nanotube fabric due to attractive forces caused by the van der Waals forces after the carbon nanotube fabric makes contact with the lower electrode or the upper electrode. Accordingly, programming is deteriorated and operations are erased of the memory device.
Furthermore, predetermined charges are continuously supplied to the lower electrode and the carbon nanotube fabric or the upper electrode and the carbon nanotube fabric in order to maintain a contact state between the lower electrode and the carbon nanotube fabric or the upper electrode and the carbon nanotube fabric. Therefore, power consumption of the memory device may considerably increase. When the charges are not continuously supplied, the contact state between the lower electrode and the carbon nanotube fabric or the upper electrode and the carbon nanotube fabric may not be maintained such that the programming and erasing operations of the memory device may not be carried out.